Uniform TitleNovel flip-flop designs tolerant to soft-errors and crosstalk effects
NameJagirdar, Aditya (author), Bushnell, Michael (chair), Parashar, Manish (internal member), Sheng, Kuang (internal member), Chakraborty, Tapan (outside member), Rutgers University, Graduate School - New Brunswick,
SubjectElectrical and Computer Engineering,
Integrated circuits--Design and construction,
DescriptionThe desire to make technology faster, smaller and more affordable compels us to shrink transistors further. As we realize designs with millions of transistors, most of the existing problems increase in severity and newer problems crop up. One major new problem is Soft-Errors in logic and the result is a severe decrease in circuit reliability. This problem has been common in static memories since 1970 and, hence, fault-tolerant memory techniques are well developed. However, soft-errors today affect sequential logic as well. Interconnect crosstalk gets severe as we move towards higher operational frequencies and must be dealt in conjunction with soft-errors. In this work, we propose novel flip-flop designs, which, unlike previous designs, are immune to soft-errors and crosstalk effects during the entire Window of Vulnerability (WoV), even around the clock edge. The Crosstalk and Soft-Error Tolerant Flip-Flop (XSEUFF2) can recover from transient pulses generated in the combinational logic and on internal nodes of the master and slave latches. It is also tolerant to any signal delays arising due to crosstalk. The area, timing and power overheads of this design over Mitra's Basic Scan Flip-Flop (BSFF) are 37%, 30% and 250% while those of Mitra's Error Blocking Scan Flip-Flop (EBSFF) and Error Trapping Scan Flip-Flop (ETSFF) are 13%, 23%, 213%, 15%, 5% and 226%. The area overhead of Roy's Error Blocking Scan Hold Flip-Flop (EBSHFF) is 9% lower than that of BSFF, while the timing and power penalties are 25% and 72%, respectively. Designs of the EBSFF, ETSFF and EBSHFF are vulnerable to soft-errors affecting the master latch around the active clock edge and hence, do not provide total immunity from soft-errors, particularly around the active clock edge. Further, they are not tolerant to crosstalk effects. We also calculate overheads for more ISCAS '89 benchmark circuits and the average overhead of the XSEUFF2 is about 20%. Thus, with reasonable increase in area, timing and power penalties we design a flip-flop completely tolerant to soft-errors and crosstalk. In conjunction with the XSEUFF2, we also propose the Crosstalk Tolerant Flip-Flop (XTFF) and the XTFF2 that are immune to only crosstalk effects and incoming transients from combinational logic. They have much lower overheads and have a different level of trade-off between reliability and performance.
NoteIncludes bibliographical references (p. 44-49).
CollectionGraduate School - New Brunswick Electronic Theses and Dissertations
Organization NameRutgers, The State University of New Jersey
RightsThe author owns the copyright to this work.