TitleAn efficient architecture for detection of multiple bit upsets in processor register files
NameYueh, Wen (author), Chakraborty, Tapan (chair), Bushnell, Michael (co-chair), Parashar, Manish (internal member), Rutgers University, Graduate School - New Brunswick,
SubjectElectrical and Computer Engineering,
DescriptionWith the semiconductor industry transitioning into the next generation of deep submicron technology such as 40 nm or 32 nm CMOS technology, transistors are becoming more vulnerable to malfunction due to soft errors. Due to the reduction in the supply and threshold voltages of the transistors in this smaller geometry, soft errors can affect the state of multiple numbers of transistors simultaneously. Hence, the traditional fault model of a single event upset (SEU) due to a soft error needs to be revisited and a new fault model and an associated fault tolerant architecture for circuit structures in deep submicron technology based on multiple-bit upsets (MBUs) needs to be developed. In this reseach work, we propose a novel fault tolerant architecture for the register files in a processor that can detect the MBUs in them efficiently. In this proposed method, we compute and store the Cyclic Redundancy Check (CRC) bits of a complete register which can be 32 bits or 64 bits wide, when new data is loaded into it. The CRC bits are of smaller bit size and are stored in a soft error protected memory structure using well known conventional soft error protection mechanisms such as error-correcting codes (ECCs), etc., for memory structures. When data from a register is read, first the new CRC value is computed based on the existing data value stored in that register and compared against the original CRC value stored previously in the soft error tolerant memory structure. If there is a difference in these two CRC values an error is flagged as it shows that the data is corrupted due to a soft error either by an SEU or MBUs during the time interval between the last write and the current read operation for that register. This operation is done for reading every register in the register file. Although this method introduces timing and area overheads, they are tolerable and this method of detection scales with the increase in the number registers in the register file. Finally, we present simulation results regarding the fault detection capability of this proposed method.
NoteIncludes bibliographical references (p. 60-62)
Noteby Wen Yueh
CollectionGraduate School - New Brunswick Electronic Theses and Dissertations
Organization NameRutgers, The State University of New Jersey
RightsThe author owns the copyright to this work.